User:Evie (Torchickens)/Sandbox: Difference between revisions
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(→Timing) |
(→Timing) |
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*"[https://gbdev.io/pandocs/STAT.html LY indicates the current horizontal line, which might be about to be drawn, being drawn, or just been drawn. LY can hold any value from 0 to 153, with values from 144 to 153 indicating the VBlank period]." |
*"[https://gbdev.io/pandocs/STAT.html LY indicates the current horizontal line, which might be about to be drawn, being drawn, or just been drawn. LY can hold any value from 0 to 153, with values from 144 to 153 indicating the VBlank period]." |
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*You can only access HRAM while a DMA transfer is taking place. |
*You can only access HRAM while a DMA transfer is taking place. |
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*One CPU cycle |
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*"[[RNG correlation (Generation I)|the rDIV register, which itself is incremented at a rate of 16384Hz (~16779Hz on SGB)]]" |
*"[[RNG correlation (Generation I)|the rDIV register, which itself is incremented at a rate of 16384Hz (~16779Hz on SGB)]]" |
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*516 cycles (2.015625 rDIV periods) - so just say 2/516 (1/258 rDIV) for one cycle. |
*516 cycles (2.015625 rDIV periods) - so just say 2/516 (1/258 rDIV) for one cycle. |
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